As background for our invention in IBM Technical Disclosure Bulletin Vol. 25, No. 3b, August 1982, entitled "I/O Pin Assignment in a Computer", there is described a method of assigning component I/O pins for physical package design based on timing information. Described is the prioritizing of nets based on timing and assigning component I/Os based on this priority. This assignment procedure has been incorporated in such tools as the IBM SHUFFLE.
A limitation of this prior method is that net priority is established exclusively by timing information. Consideration was not provided for assigning component I/O pins based on estimated wire length, or electrical constraints which in turn may affect timing.
This method results in many illegal and/or non-optimized nets, necessitating re-assignment of I/Os at one or more levels of the computer system.
The shortcomings of the prior art techniques have made it necessary to develop a comprehensive method to effectively assign component I/Os at all levels of a computer system for any technology.